开启软体

run_dc(C shell script):

/bin/rm -rf *.syn *.pvl *.mr *.svf

dc_shellXXXX -f ./xxx.tcl | tee dc_xxx.log

/bin/rm -rf *.syn *.pvl *.mr *.svf

dc_shellXXXX :开启软体xxx.tcl :合成时所下的参数，包括合成所需要使用到的 Library, Design file, 分析的需求等等。dc_xxx.log :纪录合成时的过程，透过这个档案寻找错误

xxx.tcl(Tcl script):

sh date

set sub_area_report 0
set sub_cell_report 0
set use_ultra 1

set DESIGN_NAME XXXX # set RTL module top name

Set file output destination

set RESULT_DIR "./LOG"
set REPORT_DIR "./LOG"
set DESIGN_DIR "../rtl"

source ./basic_XXX.tcl # 基本每次合成都会使用到的tcl
source ./lib.pt # Library file
source ./dc.proc.tcl # User Procedure

Check License

if { [get_license DesignWare] == 0 } { exit }
if { [get_license DC-Ultra-Opt] == 0 } { exit }
if { [get_license Power-Optimization] == 0 } { exit }

remove_design -all #清除之前合成过的东西

读取设计的档案

read_file -f verilog ../code/xxx.v
read_file -f verilog ../code/xxx.v
read_file -f verilog ../code/xxx.v
read_file -f verilog ../code/xxx.v

current_design "XXXX" # set RTL module top name

link # 确认汇入的档案 0:有问题 1:没问题
check_design

set_wire_load_mode enclosed # Sets the wire_load_model_mode attribute on the current design, specifying how wire load models are to be used to calculate wire capacitance in nets.

set_fix_multiple_port_nets -all -buffer_constants # Sets the fix_multiple_port_nets attribute to a specified value on the current design or a list of designs. This attribute controls whether compile inserts extra logic into the design to ensure that there are no feedthroughs, or that there are no two output ports connected to the same net at any level of hierarchy.

设定 System clock

create_clock -period 100 -name CLK1 [get_ports CLK1]
set_fix_hold [get_ports CLK1]
set_dont_touch_network [get_ports CLK1]

create_clock -period 33 -name CLK2 [get_ports CLK2]
set_fix_hold [get_ports CLK2]
set_dont_touch_network [get_ports CLK2]

所使用的频率，是经过除频器或DFF产生的话，使用此指令设定

create_generated_clock -name CLK3 -source CLK2 \ -divide_by 2046 [get_pins TOP/div1/o_clk]

确定设定的 Clock 是否正确，汇出资料到指定的资料夹中。

report_clock > ./Rpt/report_clock.log
check_timing > ./Rpt/check_timing.log

current_design "XXX_DIP"
set_dont_touch { *NOTOUCH* } # 所设定的NOTOUCH讯号，合成时不要被置换掉

set in/output delay

set_input_delay -clock CLK1 -clock_fall 0.3 [get_ports CLK1]

set_input_delay -clock CLK2 -clock_fall 0.3 [get_ports CLK2]

set_output_delay -clock CLK2 -clock_fall 0.3 [get_ports XXX_o]

因为两个 Clock 非同步，设定不去分析跨时钟的 path

set_false_path -from [get_clocks CLK1] -to [get_clocks CLK2]

set_false_path -from [get_clocks CLK2] -to [get_clocks CLK1]

让同一个 net 接到两个以上的 port 时，自动加 buffer 来帮助推动。

set_fix_multiple_port_nets -feedthroughs
set_fix_multiple_port_nets -all -buffer_constants

The following is setting for compile_ultra

if { $use_ultra == 1 } {
set hlo_resource_allocation constraint_driven # 资源共享 : 不开
set hlo_resource_implementation use_fastest # 实际合成 : 速度
set hlo_minimize_tree_delay true # 最小化的clock tree delay
set hlo_share_common_sub_expressions true
set compile_use_low_timing_effort false # 如果开启可以加速编译(几乎可以回到线性模型的速度)，但是会影响準确性
set compile_implementation_selection true #在 compiler 期间，重新评估 Library 实现的选择(re-eval of synthetic library implementation selections during the
compile. )
}

常量register优化掉，FM又能PASS

set compile_seqmap_propagate_constants false #默认值true。。控制编译命令是否尝试识别和删除常量寄存器，并且在整个过程中传播常量值。Controls whether the compile command tries toi dentify and remove constant registers and propagate the constant value throughout the design. When the value is true (the default), compile tries to identify and remove constant sequential elements in the design, which improves the area of the design.

set compile_seqmap_propagate_high_effort false

compile_ultra -no_seq_output_inversion -no_autoungroup -exact_map -no_boundary_optimization

#-no_autoungroup : 不会打散底层的Module。不加的话，DC会根据优化情况调整层次，时序也许会好一点，但是要找讯号线不好找

#-no_seq_output_inversion :和寄存器输出端选Q还是QN有关。

#-exact_map :Specifies that sequential cells are mapped exactly as indicated in HDL.

#-no_boundary_optimization : Specifies that no hierarchical boundary optimization is to be performed. By default, boundary optimization is turned on during compile_ultra activity.

报出面积

redirect -append ./Log/XXX_DIP_syn.area.high { report_area }

current_design "XXX_DIP"

link
check_design

Change Naming Rule

define_name_rules name_rule -allowed "a-z A-Z 0-9 _" -max_length 255 -type cell
define_name_rules name_rule -allowed "a-z A-Z 0-9 _[]" -max_length 255 -type net
define_name_rules name_rule -map {{"\\*cell\\*" "cell"}}
change_names -hierarchy -rules name_rule
change_names -rule verilog -h

设定面积大小的单位

set BASE_CELL Lib_3p3v_WORST/NAND

p_hier_area \
$DESIGN_NAME 2 \
[get_att [get_lib_cells ${BASE_CELL}] area] \
${REPORT_DIR}/XXX_DIP.hier2_area.rpt

输出档案

write_sdc ./output/XXX_DIP_syn_out.sdc
write_sdf -context verilog ./output/XXX_DIP_syn.sdf
write -f verilog -hier -o ./output/XXX_DIP_syn_netlist.v

redirect -append ./Log/XXX_DIP_syn.desgin { report_design }
redirect -append ./Log/XXX_DIP_syn.area { report_area -hier }
redirect -append ./Log/XXX_DIP_syn.cell { report_cell }
redirect -append ./Log/XXX_DIP_syn.max.timing { report_timing -delay max -max_paths 100 -sign 5}
redirect -append ./Log/XXX_DIP_syn.min.timing { report_timing -delay min -max_paths 100 -sign 5}
redirect -append ./Log/XXX_DIP_syn.max.timing { report_timing -delay max -max_paths 10000 -nets -cap -tran}

sh date